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EL2142
Data Sheet February 11, 2005 FN7049.1
Differential Line Receiver
The EL2142 is a very high bandwidth amplifier designed to extract the difference signal from noisy environments, and is thus primarily targeted for applications such as receiving signals from twisted pair lines, or any application where common mode noise injection is likely to occur. The EL2142 is stable for a gain of one, and requires two external resistors to set the voltage gain. The output common mode level is set by the reference pin (VREF), which has a -3dB bandwidth of over 100MHz. Generally, this pin is grounded, but it can be tied to any voltage reference. The output can deliver a minimum of 50mA and is short circuit protected to withstand a temporary overload condition.
Features
* Differential input range 2.3V * 150MHz 3dB bandwidth * 400V/s slewrate * 5V supplies or single supply * 50mA minimum output current * Output swing (100 load) to within 1.5V of supplies * Low power-11mA typical supply current * Pb-free available (RoHS compliant)
Applications
* Twisted pair receiver * Differential line receiver * VGA over twisted pair
Ordering Information
PART NUMBER EL2142CS EL2142CS-T7 EL2142CS-T13 EL2142CSZ (See Note) EL2142CSZ-T7 (See Note) EL2142CSZT13 (See Note) PACKAGE 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC (Pb-free) 8-pin SOIC (Pb-free) 8-pin SOIC (Pb-free) TAPE & REEL 7" 13" 7" 13" PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027
* ADSL/HDSL receiver * Differential to single ended amplification. * Reception of analog signals in a noisy environment.
Pinout
EL2142 (8-PIN SOIC) TOP VIEW
NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1998, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL2142
Absolute Maximum Ratings (TA = 25C)
Supply Voltage (VCC-VEE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C Recommended Operating Temperature . . . . . . . . . . . -40C to 85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER VSUPPLY IS VOS IIN ZIN CIN VDIFF AVOL VIN VOUT IOUT(min) VN VREF PSRR CMRR2 CMRR1
VCC = +5V, VEE = -5V, TEE = 25C, VIN= 0V, RL = 100, unless otherwise specified DESCRIPTION MIN 3.0 TYP 5.0 11 -25 -20 10 6 400 1 2.0 2.3 75 -2.6 2.9 50 3.1 60 36 -2.5 60 60 50 70 70 60 +3.3 +4.0 MAX 6.3 14 40 20 UNITS V mA mV A k pF V dB V V mA nV/Hz V dB dB dB
Supply Operating Range (VCC-VEE) Power Supply Current (no load) Input Referred Offset Voltage Input Bias Current (VIN, VINB, VREF) Differential Input Resistance Differential Input Capacitance Differential Input Range Open Loop Voltage Gain Input Common Mode Voltage Range Output Voltage Swing (50 load to GND) Minimum Output Current Input Referred Voltage Noise Output Voltage Control Range Power Supply Rejection Ratio Input Common Mode Rejection Ratio (VIN= 2V) Input Common Mode Rejection Ratio (full VIN range)
AC Electrical Specifications
PARAMETER BW(-3dB) SR TSTL GBWP VREFBW(-3dB) VREFSR dG d
VCC = +5V, VEE = -5V, TA = 25C, VIN = 0V, RLOAD = 100, unless otherwise specified DESCRIPTION MIN TYP 150 400 15 200 130 100 0.2 0.2 MAX UNITS MHz V/s ns MHz MHz V/sec %
-3dB Bandwidth (Gain =1) Slewrate Settling time to 1% Gain bandwidth product VREF -3dB Bandwidth VREF Slewrate Differential gain at 3.58MHz Differential phase at 3.58MHz
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FN7049.1 February 11, 2005
EL2142 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 PIN NAME VFB VIN VINB VREF NC VCC VEE VOUT Positive supply voltage Negative supply voltage Output voltage Feedback input Non-inverting input Inverting input Sets output voltage level to VREF when VIN=VINB FUNCTION
Typical Performance Curves
IS vs Supply Voltage Frequency Response (Gain = 1)
Frequency Response vs Resistor R1 (Gain = 4)
CMRR vs Frequency
VREF Frequency Response
Distortion vs Frequency (Gain = 3, RLOAD = 100) VIN = 2VPK-PK
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FN7049.1 February 11, 2005
EL2142 Applications Information
one, there is little to be gained from choosing resistor R1 value below 200, for it would only result in increased power dissipation and potential signal distortion. Above 200, the bandwidth response will develop some peaking (for a gain of one), but substantially higher R1 values may be used for higher voltage gains, such as up to 1k at a gain of four before peaking will develop.
Capacitance Considerations
As with many high bandwidth amplifiers, the EL2142 prefers not to drive highly capacitive loads. It is best if the capacitance on VOUT is kept below 10pF if the user does not want gain peaking to develop. The VFB node forms a potential pole in the feedback loop, so capacitance should be minimized on this node for maximum bandwidth. The amount of capacitance tolerated on any of these nodes in an actual application will also be dependent on the gain setting and the resistor values in the feedback network.
Gain Equation
VOUT = ((R2+R1)/R1) x (VIN-VINB+VREF) when R1 tied to GND VOUT = ((R2+R1)/R1) x (VIN-VINB) when R1 tied to VREF
Choice of Feedback Resistor
For a gain of one, VOUT may be shorted back to VFB, but 100-200 improves the bandwidth. For gains greater than
Typical Applications Circuits
100 50 VFB VIN EL2142 VINB 50 VREF VOUT
FIGURE 1. TYPICAL TWISTED PAIR APPLICATION
FIGURE 2. COAXIAL CABLE DRIVER PAIR APPLICATION
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FN7049.1 February 11, 2005
EL2142
FIGURE 3. SINGLE SUPPLY RECEIVER
R3
R1 C1
R2
50 Z0 = 100
VFB VIN EL2142 VINB VOUT
50
VREF
FIGURE 4. COMPENSATED LINE RECEIVER
FIGURE 5. TWO CHANNEL MULTIPLEXER
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FN7049.1 February 11, 2005
EL2142 SOIC Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 6
FN7049.1 February 11, 2005

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